Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

In this paper we present a prototype continuous time Σ∆-modulator in a 0.35 μm technology. The circuit has a 6-bit internal quantizer. Through the combination of a modified architecture and comparator interpolation this high quantizer resolution is achieved with only 15 comparators. However, it turns out that this approach imposes a severe speed constraint on the analog adder circuit. The modulator consists of a 3rd order loop and special care was taken in the design of the loop filter. The presented design has two particular features. First an explicit and controlled delay of 0.25 times the sampling period is introduced in the loop. Second, the Nyquist stability criterion and the vector gain margin are adopted to design a robustly stable modulator loop filter. This way our modulator does not require any tuning or trimming of the filter coefficients. Measurement results show a Peak SNR of 82 dB and a dynamic range of 85 dB for a bandwidth of 1.5 MHz.